Simon O'Shea
48 lines
2.8 KiB
Plaintext
48 lines
2.8 KiB
Plaintext
Welcome to the LC-3 in Logism!
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This processing unit can perform basic arithmetic, logic, and memory operations.
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The following instructions are supported: ADD, AND, NOT, LD, LDR, ST, and STR. Here is an example list
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of some pre-tested instructions that you can perform (in no particular order):
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1401 = ADD R2, R0, R1
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1883 = ADD R4, R2, R3
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c000 = JMP R0
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260a = LD R3 #10
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6649 = LDR R3 R1 #9
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3403 = ST R2 #3
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778a = STR R3 R6 #10
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To run any of these instructions: enter the 4-digit hex-code(s) into the RAM unit found in the
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'main' circuit, enter values into the appropriate registers found within the 'Registers' circuit
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to be operated on, and begin ticking the clock. To restart the system, use the hand that allows
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you to change values (ctrl+1) and double click on the magnifying glass to enter the controlUnit.
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Within the controlUnit, reset the 'phaseCounter' and the register labeled 'PC' to 0 and then
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you're good to go.
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To note when using this processor: any ST instruction (not STR) should use an offset value of one-
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less than the offset that would get to the address you want to store at. The order in which the phases
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change data causes the 'pcSelector' to receive an already-incremented PC value, so when the offset is
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added during phase 3, the destination value is written one spot above the originally intended address.
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Also, if the Logisim gives a 'label collision' error when loading the circuit, just rename any of the
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tunnels that output blue wires in the 'main' circuit to 'clock'. Otherwise, everything should work as
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intended.
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All of the tests listed above were previously tested with various register values and proved to work
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as intended. The AND and NOT operations were also tested early in the building process and once the
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ALU was completed it has not been modified so there was no reason to retest. The LD and LDR operations
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properly read from the address instructed and store to the correct register, ST stores the value found
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within the source register but the offset needs to be subtracted by one to store to the proper address,
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and STR stores the value found within the source register to the intended address without any
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accommodations to the offset or base register. Since all of these worked as intended, I came to the
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conclusion that they were good tests. I also ran a string of instructions in a row that read a value,
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added two values together, jumped ahead 30 addresses, and then stored a value 3 addresses ahead of the
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PC, and after several full phase cycles the PC incremented properly up to the stored value from the
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store address. Everything worked as far as I could tell and I think that these are good tests for the
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instructions.
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All circuits were designed to be easy to follow and feature documentation describing some of the specific
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aspects of the system.
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